Among the many verification challenges confronting system-on-chip designers these days, clock domain crossings (CDCs) rank near the top in difficulty. Two particularly troublesome CDC-related issues ...

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

This application note explains the internal architecture of the asynchronous FIFO made by Cypress (CY7C421) and its functionality – the writing and reading process. It also discusses FIFO ...

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet ...