Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Some digital design and verification engineers imagine that their colleagues working on analog/mixed-signal (AMS) chips are jealous. After all, the digital development flow has enjoyed the benefits of ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...

Agentic AI shifts RTL verification from tool automation to workflow intelligence, reducing coordination overhead.

As the cost of chip turns has grown from thousands to millions of dollars, missed design bugs are unacceptable Chip design verification used to be straightforward, if not always easy. Verification ...

In chip design, the answer is not always available in any textbook. Students often need to test, troubleshoot, modify and ...

Completing Clock Domain Crossing Verification. Nvidia wanted a methodology for complete clock domain crossing verification ...

People freely interchange the terms “test” and “verification.” It’s understandable when terms like testcase, testbench and device under test (DUT) are in conjunction with different types of ...