ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has unveiled the latest release of its HES-DVM™ ...

Semiconductor Engineering sat down to explore partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced automatic FPGA partitioning to ...

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a ...

With up to 21 Xilinx Virtex-5 FPGAs, the CHIPit Platinum V5 prototyping system can handle ASIC and system-on-a-chip (SoC) designs of up to 28 Mgates. The system targets users who need early hardware ...

As the size of the verification task for SoCs continues to balloon, more verification teams are turning to some sort of hardware emulation to increase the number of cycles they can run. But emulation ...

With the emergence of 90-nm process technology, ASIC designers get to explore uncharted levels of performance and density. However, it has also unleashed a slew of challenging design-integrity issues, ...